@inproceedings{joseph2006a,
author = {Joseph, P. J. and Vaswani, Kapil and Thazuthaveetil, Matthew J.},
title = {A Predictive Performance Model for Superscalar Processors},
booktitle = {Proceedings of the International Symposium on Microarchitecture (MICRO)},
year = {2006},
month = {January},
abstract = {Designing and optimizing high performance microprocessors is an increasingly difficult task due to the size and complexity of the processor design space, high cost of detailed simulation and several constraints that a processor design must satisfy. In this paper, we propose the use of empirical non-linear modeling techniques to assist processor architects in making design decisions and resolving complex trade-offs. We propose a procedure for building accurate non-linear models that consists of the following steps: (i) selection of a small set of representative design points spread across process or design space using latin hypercube sampling, (ii) obtaining performance measures at the selected design points using detailed simulation, (iii) building non-linear models for performance using the function approximation capabilities of radial basis function networks, and (iv) validating the models using an independently and randomly generated set of design points. We evaluate our model building procedure by constructing non-linear performance models for programs from the SPEC CPU2000 benchmark suite with a micro-architectural design space that consists of 9 key parameters. Our results show that the models, built using a relatively small number of simulations, achieve high prediction accuracy (only 2.8%error in CPI estimates on average) across a large processor design space. Our models can potentially replace detailed simulation for common tasks such as the analysis of key micro-architectural trends or searches for optimal processor design points.},
url = {http://approjects.co.za/?big=en-us/research/publication/a-predictive-performance-model-for-superscalar-processors/},
edition = {Proceedings of the International Symposium on Microarchitecture (MICRO)},
}