@inproceedings{xia2018cherirtos,
author = {Xia, Hongyan and Woodruff, Jonathan and Barral, Hadrien and Esswood, Lawrence and Joannou, Alexandre and Kovacsics, Robert and Chisnall, David and Roe, Michael and Davis, Brooks and Napierala, Edward and Baldwin, John and Gudka, Khilan and Neumann, Peter G. and Richardson, Alex and Moore, Simon W. and Watson, Robert N. M.},
title = {CheriRTOS: A Capability Model for Embedded Devices},
organization = {IEEE},
booktitle = {Proceedings of the 2018 IEEE 36th International Conference on Computer Design (ICCD)},
year = {2018},
month = {October},
abstract = {—Embedded systems are deployed ubiquitously among various sectors including automotive, medical, robotics and avionics. As these devices become increasingly connected, the attack surface also increases tremendously; new mechanisms must be deployed to defend against more sophisticated attacks while not violating resource constraints. In this paper we present
CheriRTOS on CHERI-64, a hardware-software platform atop Capability Hardware Enhanced RISC Instructions (CHERI) for embedded systems.

Our system provides efficient and scalable task isolation, fast and secure inter-task communication, fine-grained memory safety, and real-time guarantees, using hardware capabilities as the sole protection mechanism. We summarize state-of-the-art security and memory safety for embedded systems for comparison with our platform, illustrating the superior substrate provided by CHERI’s capabilities. Finally, our evaluations show that a capability system can be implemented within the constraints of embedded systems.},
url = {http://approjects.co.za/?big=en-us/research/publication/cherirtos-a-capability-model-for-embedded-devices/},
}