{"id":152315,"date":"1998-02-01T00:00:00","date_gmt":"1998-02-01T00:00:00","guid":{"rendered":"https:\/\/www.microsoft.com\/en-us\/research\/msr-research-item\/asymmetric-real-time-scheduling-on-a-multimedia-processor\/"},"modified":"2018-10-16T22:07:00","modified_gmt":"2018-10-17T05:07:00","slug":"asymmetric-real-time-scheduling-on-a-multimedia-processor","status":"publish","type":"msr-research-item","link":"https:\/\/www.microsoft.com\/en-us\/research\/publication\/asymmetric-real-time-scheduling-on-a-multimedia-processor\/","title":{"rendered":"Asymmetric Real Time Scheduling on a Multimedia Processor"},"content":{"rendered":"<div class=\"asset-content\">\n<p>This paper describes the hardware and system software support for multi-tasking a dual-processor used in a multimedia system. One of the two processors is a conventional RISC processor, the other is a vector processor of new design. There is no commonality in the instruction sets of the two processors. We schedule the former preemptively and the latter cooperatively via check points, resulting in an asymmetric scheduling algorithm. Media processing requires predictable scheduling behaviors. Programmers can inform our scheduler of the Real Time requirements of their computations using time-constraints. Scheduling decisions are very fine-grained, and place strong efficiency demands on the system implementation.<\/p>\n<\/div>\n<p><!-- .asset-content --><\/p>\n","protected":false},"excerpt":{"rendered":"<p>This paper describes the hardware and system software support for multi-tasking a dual-processor used in a multimedia system. One of the two processors is a conventional RISC processor, the other is a vector processor of new design. There is no commonality in the instruction sets of the two processors. We schedule the former preemptively and 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