Speedups of coupled processor-FPGA systems over traditional microprocessor systems are limited by the cost of hardware recon\ufb01guration. In this paper we compare several new con\ufb01guration caching algorithms that reduce the latency of recon\ufb01guration. We also present a cache replacement strategy for a 3-level hierarchy. Using the techniques we present, total latency for loading the con\ufb01gurations is reduced, lowering the con\ufb01gurable overhead.<\/p>\n","protected":false},"excerpt":{"rendered":"
Speedups of coupled processor-FPGA systems over traditional microprocessor systems are limited by the cost of hardware recon\ufb01guration. In this paper we compare several new con\ufb01guration caching algorithms that reduce the latency of recon\ufb01guration. We also present a cache replacement strategy for a 3-level hierarchy. Using the techniques we present, total latency for loading the con\ufb01gurations […]<\/p>\n","protected":false},"featured_media":0,"template":"","meta":{"msr-url-field":"","msr-podcast-episode":"","msrModifiedDate":"","msrModifiedDateEnabled":false,"ep_exclude_from_search":false,"_classifai_error":"","footnotes":""},"msr-content-type":[3],"msr-research-highlight":[],"research-area":[13547],"msr-publication-type":[193716],"msr-product-type":[],"msr-focus-area":[],"msr-platform":[],"msr-download-source":[],"msr-locale":[268875],"msr-post-option":[],"msr-field-of-study":[],"msr-conference":[],"msr-journal":[],"msr-impact-theme":[],"msr-pillar":[],"class_list":["post-155354","msr-research-item","type-msr-research-item","status-publish","hentry","msr-research-area-systems-and-networking","msr-locale-en_us"],"msr_publishername":"Springer-Verlag","msr_edition":"FPL '01: Proceedings of the 11th International Conference on Field-Programmable Logic and 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