{"id":159453,"date":"2010-07-01T00:00:00","date_gmt":"2010-07-01T00:00:00","guid":{"rendered":"https:\/\/www.microsoft.com\/en-us\/research\/msr-research-item\/blas-comparison-on-fpga-cpu-and-gpu\/"},"modified":"2018-10-16T22:04:21","modified_gmt":"2018-10-17T05:04:21","slug":"blas-comparison-on-fpga-cpu-and-gpu","status":"publish","type":"msr-research-item","link":"https:\/\/www.microsoft.com\/en-us\/research\/publication\/blas-comparison-on-fpga-cpu-and-gpu\/","title":{"rendered":"BLAS Comparison on FPGA, CPU and GPU"},"content":{"rendered":"<div class=\"asset-content\">\n<p>High Performance Computing (HPC) or scientific codes are being executed across a wide variety of computing platforms from embedded processors to massively parallel GPUs. We present a comparison of the Basic Linear Algebra Subroutines (BLAS) using double-precision floating point on an FPGA, CPU and GPU. On the CPU and GPU, we utilize standard libraries on state-of-the-art devices. On the FPGA, we have developed parameterized modular implementations for the dotproduct and Gaxpy or matrix-vector multiplication. In order to obtain optimal performance for any aspect ratio of the matrices, we have designed a high-throughput accumulator to perform an efficient reduction of floating point values. To support scalability to large data-sets, we target the BEE3 FPGA platform. We use performance and energy efficiency as metrics to compare the different platforms. Results show that FPGAs offer comparable performance as well as 2.7 to 293 times better energy efficiency for the test cases that we implemented on all three platforms.<\/p>\n<\/div>\n<p><!-- .asset-content --><\/p>\n","protected":false},"excerpt":{"rendered":"<p>High Performance Computing (HPC) or scientific codes are being executed across a wide variety of computing platforms from embedded processors to massively parallel GPUs. We present a comparison of the Basic Linear Algebra Subroutines (BLAS) using double-precision floating point on an FPGA, CPU and GPU. On the CPU and GPU, we utilize standard libraries on [&hellip;]<\/p>\n","protected":false},"featured_media":0,"template":"","meta":{"msr-url-field":"","msr-podcast-episode":"","msrModifiedDate":"","msrModifiedDateEnabled":false,"ep_exclude_from_search":false,"_classifai_error":"","footnotes":""},"msr-content-type":[3],"msr-research-highlight":[],"research-area":[13552],"msr-publication-type":[193716],"msr-product-type":[],"msr-focus-area":[],"msr-platform":[],"msr-download-source":[],"msr-locale":[268875],"msr-post-option":[],"msr-field-of-study":[],"msr-conference":[],"msr-journal":[],"msr-impact-theme":[],"msr-pillar":[],"class_list":["post-159453","msr-research-item","type-msr-research-item","status-publish","hentry","msr-research-area-hardware-devices","msr-locale-en_us"],"msr_publishername":"IEEE","msr_edition":"IEEE Computer Society Symposium on VLSI","msr_affiliation":"","msr_published_date":"2010-07-01","msr_host":"","msr_duration":"","msr_version":"","msr_speaker":"","msr_other_contributors":"","msr_booktitle":"IEEE Computer Society Symposium on VLSI","msr_pages_string":"","msr_chapter":"","msr_isbn":"","msr_journal":"","msr_volume":"","msr_number":"","msr_editors":"","msr_series":"","msr_issue":"","msr_organization":"","msr_how_published":"","msr_notes":"","msr_highlight_text":"","msr_release_tracker_id":"","msr_original_fields_of_study":"","msr_download_urls":"","msr_external_url":"","msr_secondary_video_url":"","msr_longbiography":"","msr_microsoftintellectualproperty":1,"msr_main_download":"221314","msr_publicationurl":"","msr_doi":"","msr_publication_uploader":[{"type":"file","title":"ISVLSI_FINAL.pdf","viewUrl":"https:\/\/www.microsoft.com\/en-us\/research\/wp-content\/uploads\/2010\/07\/ISVLSI_FINAL.pdf","id":221314,"label_id":0}],"msr_related_uploader":"","msr_attachments":[{"id":221314,"url":"https:\/\/www.microsoft.com\/en-us\/research\/wp-content\/uploads\/2010\/07\/ISVLSI_FINAL.pdf"}],"msr-author-ordering":[{"type":"text","value":"Srinidhi Kestur","user_id":0,"rest_url":false},{"type":"user_nicename","value":"joda","user_id":32353,"rest_url":"https:\/\/www.microsoft.com\/en-us\/research\/wp-json\/microsoft-research\/v1\/researchers?person=joda"},{"type":"user_nicename","value":"olliew","user_id":33155,"rest_url":"https:\/\/www.microsoft.com\/en-us\/research\/wp-json\/microsoft-research\/v1\/researchers?person=olliew"}],"msr_impact_theme":[],"msr_research_lab":[],"msr_event":[],"msr_group":[],"msr_project":[169466],"publication":[],"video":[],"download":[],"msr_publication_type":"inproceedings","related_content":{"projects":[{"ID":169466,"post_title":"BEE3","post_name":"bee3","post_type":"msr-project","post_date":"2008-02-26 11:25:38","post_modified":"2017-06-01 18:42:27","post_status":"publish","permalink":"https:\/\/www.microsoft.com\/en-us\/research\/project\/bee3\/","post_excerpt":"The BEE3 (Berkeley Emulation Engine, version 3) is a multi-FPGA system with up to 64 GB of DRAM and several I\/O subsystems that can be used to enable faster, larger and higher fidelity computer architecture or other systems research. Objective: Revitalizing Computer Architecture Research The Problem Computer Architecture is increasingly incremental, and boring. Many papers study a tiny feature, and report 5% improvements. Simulation is too slow to allow full-system experiments running real software. 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