Previous research has shown that Explicit Data Graph Execution (EDGE) instruction set architectures (ISA) allow for power ef\ufb01cient performance scaling. In this paper we describe the preliminary design of a new dynamic multicore processor called E2 that utilizes an EDGE ISA to allow for the dynamic composition of physical cores into logical processors. We provide details of E2\u2019s support for dynamic recon\ufb01gurability and show how the EDGE ISA facilities out-of-order vector execution.<\/p>\n","protected":false},"excerpt":{"rendered":"
Previous research has shown that Explicit Data Graph Execution (EDGE) instruction set architectures (ISA) allow for power ef\ufb01cient performance scaling. In this paper we describe the preliminary design of a new dynamic multicore processor called E2 that utilizes an EDGE ISA to allow for the dynamic composition of physical cores into logical processors. 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