{"id":166444,"date":"2006-01-01T00:00:00","date_gmt":"2006-01-01T00:00:00","guid":{"rendered":"https:\/\/www.microsoft.com\/en-us\/research\/msr-research-item\/area-performance-trade-offs-in-tiled-dataflow-architectures\/"},"modified":"2018-10-16T20:18:01","modified_gmt":"2018-10-17T03:18:01","slug":"area-performance-trade-offs-in-tiled-dataflow-architectures","status":"publish","type":"msr-research-item","link":"https:\/\/www.microsoft.com\/en-us\/research\/publication\/area-performance-trade-offs-in-tiled-dataflow-architectures\/","title":{"rendered":"Area-Performance Trade-offs in Tiled Dataflow Architectures"},"content":{"rendered":"<p>Tiled architectures, such as RAW, SmartMemories, TRIPS, and WaveScalar, promise to address several issues facing conventional processors, including complexity, wire-delay, and performance. The basic premise of these architectures is that larger, higher-performance implementations can be constructed by replicating the basic tile across the chip. This paper explores the area-performance trade-offs when designing one such tiled architecture, WaveScalar. We use a synthesizable RTL model and cycle-level simulator to perform an area\/performance pareto analysis of over 200 WaveScalar processor designs ranging in size from 19mm<sup>2<\/sup> to 575mm<sup>2<\/sup> and having a 22 FO4 cycle time. We demonstrate that, for multi-threaded workloads, WaveScalar performance scales almost ideally from 19 to 101mm <sup>2<\/sup> when optimized for area efficiency and from 44 to 202mm<sup>2<\/sup> when optimized for peak performance. Our analysis reveals that WaveScalar&#8217;s hierarchical interconnect plays an important role in overall scalability, and that WaveScalar achieves the same (or higher) performance in substantially less area than either an aggressive out-of-order superscalar or Sun&#8217;s Niagara CMP processor.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Tiled architectures, such as RAW, SmartMemories, TRIPS, and WaveScalar, promise to address several issues facing conventional processors, including complexity, wire-delay, and performance. The basic premise of these architectures is that larger, higher-performance implementations can be constructed by replicating the basic tile across the chip. This paper explores the area-performance trade-offs when designing one such tiled [&hellip;]<\/p>\n","protected":false},"featured_media":0,"template":"","meta":{"msr-url-field":"","msr-podcast-episode":"","msrModifiedDate":"","msrModifiedDateEnabled":false,"ep_exclude_from_search":false,"footnotes":""},"msr-content-type":[3],"msr-research-highlight":[],"research-area":[13561,13560],"msr-publication-type":[193716],"msr-product-type":[],"msr-focus-area":[],"msr-platform":[],"msr-download-source":[],"msr-locale":[268875],"msr-field-of-study":[],"msr-conference":[],"msr-journal":[],"msr-impact-theme":[],"msr-pillar":[],"class_list":["post-166444","msr-research-item","type-msr-research-item","status-publish","hentry","msr-research-area-algorithms","msr-research-area-programming-languages-software-engineering","msr-locale-en_us"],"msr_publishername":"IEEE Computer Society","msr_edition":"Proceedings of the 33rd Annual International Symposium on Computer Architecture","msr_affiliation":"","msr_published_date":"2006-01-01","msr_host":"","msr_duration":"","msr_version":"","msr_speaker":"","msr_other_contributors":"","msr_booktitle":"Proceedings of the 33rd Annual International Symposium on Computer Architecture","msr_pages_string":"314\u2013326","msr_chapter":"","msr_isbn":"0-7695-2608-X","msr_journal":"","msr_volume":"","msr_number":"","msr_editors":"","msr_series":"ISCA '06","msr_issue":"","msr_organization":"","msr_how_published":"","msr_notes":"","msr_highlight_text":"","msr_release_tracker_id":"","msr_original_fields_of_study":"","msr_download_urls":"","msr_external_url":"","msr_secondary_video_url":"","msr_longbiography":"","msr_microsoftintellectualproperty":1,"msr_main_download":"","msr_publicationurl":"http:\/\/ieeexplore.ieee.org\/xpl\/articleDetails.jsp?arnumber=1635962","msr_doi":"10.1109\/ISCA.2006.10","msr_publication_uploader":[{"type":"url","title":"http:\/\/ieeexplore.ieee.org\/xpl\/articleDetails.jsp?arnumber=1635962","viewUrl":false,"id":false,"label_id":0},{"type":"doi","title":"10.1109\/ISCA.2006.10","viewUrl":false,"id":false,"label_id":0}],"msr_related_uploader":"","msr_attachments":[{"id":0,"url":"http:\/\/ieeexplore.ieee.org\/xpl\/articleDetails.jsp?arnumber=1635962"}],"msr-author-ordering":[{"type":"text","value":"Steven Swanson","user_id":0,"rest_url":false},{"type":"user_nicename","value":"anputnam","user_id":31049,"rest_url":"https:\/\/www.microsoft.com\/en-us\/research\/wp-json\/microsoft-research\/v1\/researchers?person=anputnam"},{"type":"text","value":"Martha Mercaldi","user_id":0,"rest_url":false},{"type":"text","value":"Ken Michelson","user_id":0,"rest_url":false},{"type":"text","value":"Andrew Petersen","user_id":0,"rest_url":false},{"type":"text","value":"Andrew Schwerin","user_id":0,"rest_url":false},{"type":"text","value":"Mark Oskin","user_id":0,"rest_url":false},{"type":"text","value":"Susan J. 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