{"id":1163453,"date":"2026-03-06T07:39:05","date_gmt":"2026-03-06T15:39:05","guid":{"rendered":"https:\/\/www.microsoft.com\/en-us\/research\/?post_type=msr-video&p=1163453"},"modified":"2026-03-06T07:39:06","modified_gmt":"2026-03-06T15:39:06","slug":"cross-leveraging-ai-asics-for-homomorphic-encryption","status":"publish","type":"msr-video","link":"https:\/\/www.microsoft.com\/en-us\/research\/video\/cross-leveraging-ai-asics-for-homomorphic-encryption\/","title":{"rendered":"CROSS \u2014 Leveraging AI ASICs for Homomorphic Encryption"},"content":{"rendered":"\n
Artificial Intelligence (AI) is driving a new industrial revolution, transforming human workflows increasingly into digital tokens, i.e., tokenizing the entire world. However, this transformation exposes sensitive data at an unprecedented scale, leading to heavy privacy breaches that\u00a0stalled AI’s adoption. Homomorphic Encryption (HE) provides strong data privacy for cloud services but at the cost of prohibitive computational overhead. While GPUs have emerged as a practical platform for accelerating, HE, there remains an order-of-magnitude energy-efficiency gap compared to specialized (but expensive) HE ASICs. This talk explores an alternate direction: leveraging existing AI accelerators, like Google’s TPUs, to accelerate homomorphic encryption and broadly cryptography primitives. The key focus is the advanced compilation techniques that could transform “any application with static scheduling of modular arithmetic\u201d into kernels natively supported by AI ASICs such TPU\u00a0without any hardware modification for acceleration. Our evaluation shows that CROSS achieving the SoTA throughput in NTT and HE operators, SoTA energy efficiency among commodity devices including CPUs, GPUs and FPGAs.<\/p>\n\n\n\n
TL;DR: CROSS is the first project to demonstrate that Homomorphic Encryption operators with static scheduling of modular arithmetic could be transformed into kernels suitable for TPU, inheriting the SoTA energy efficiency and throughput of modern AI ASICs without any hardware modification. This paves the road for accelerating broad cryptography primitives on AI ASICs like Google\u2019s TPU, sparking a new direction of hardware-friendly protocol design.<\/p>\n\n\n\n