Optics for the Cloud Research Alliance

TU/e PIs: Xaveer Leijtens (opens in new tab), Kevin Williams (opens in new tab)

Microsoft PI: Kai Shi

TU/e Student: Wenjing Tian (opens in new tab)

The exponential rise in data consumption in the cloud is now pushing data centers beyond their limits. Optical interconnect can be an alternative technology to boost the ever-evolving cloud. Optical switching using photonic integrated circuits holds the promise of flexibility, low latency, connectivity, and energy efficiency. However, the assembly of integrated photonic switches is one of the greatest barriers to deploying optical switch technology. In this work, we investigate the assembly method for photonic integrated circuits using hybrid integration across two photonic integration platforms, Indium Phosphide (InP), and Silicon Nitride (SiN) based TriPleX. The assembly method is suited to flip-chip attachment which offers a cost-effective solution for low loss and high port count fiber-to-chip coupling.

EPFL PI: Tobias Kippenberg (opens in new tab)

Microsoft PI: Sophie Lange (opens in new tab)

EPFL Student: Arslan Raja (opens in new tab)

The sub-nanoseconds (less than 550 ps) optical switching is achieved by using a multiwavelength source based on a soliton microcomb (Si3N4) and wavelength selector based on a semiconductor optical amplifier. The optical switching systems with 25 GBd NRZ and PAM4 burst mode transmission are demonstrated.

ICL PIs: Mark Neil (opens in new tab), Matthew Foreman (opens in new tab)

Microsoft PI: James Clegg

ICL Student: Zhonghe Feng (opens in new tab)

Measuring birefringence in 3D is important for many applications including optical data storage and cell biology. The current state-of-the-art techniques use methods that are designed to measure thin (2D) structures but have been adapted in ad-hoc ways and combined with advanced processing to recover 3D information. Remarkably, there is an important and basic research question that still exists: is there a physically correct way to isolate and measure the birefringence of a thin 2D layer that is contained within a 3D volume, and therefore correctly reconstruct a full 3D volume? This PhD research project will answer this question.

UCL PIs: Polina Bayvel (opens in new tab), Robert Killey (opens in new tab), George Zervas (opens in new tab)

Microsoft PIs: Christos Gkantsidis, Fotini Karinou

UCL Student: Hubert Dzieciol (opens in new tab)

Signal design strategies to improve phase noise tolerance of a short-range coherent system such as 400ZR and beyond. We propose a low-complexity approach demonstrating up to .7dB gains (both GMI and post-FEC) when compared to 16QAM constellations and 0.4dB for AWGN optimal formats.

UCL PIs: Polina Bayvel (opens in new tab), George Zervas (opens in new tab)

Microsoft PI: Benn Thomsen

UCL Student: Thomas Gerard (opens in new tab)

The aim of this PhD project was to develop an intelligent transmitter that can enable the creation of all-optical architectures for flat, scalable, high bandwidth data centre networks. The transmitter must exceed the capabilities of existing designs, providing 2 orders of magnitude improvement in switch time (sub-nanosecond), scalable tuning bandwidths covering the C-band and beyond, and power efficient modulation for high link-budget networks. To that end, the thesis investigated four main areas: (1) Determine the transceiver characteristics needed to create scalable wavelength routed networks supporting >105 servers using real time, space- and wavelength-switched optical transceivers operating at 25Gb/s. (2) Investigation of artificial intelligent methods for commercial tuneable laser optimisation, guaranteeing fast and reliable wavelength switching. (3) Development of novel wavelength tuneable subsystems that can approach and overcome the tuning speeds and bandwidth limits of traditional tuneable laser sources, achieving sub-ns switching across greater-than-C-band frequencies. (4) Investigation of novel transmitter architectures that maximize link loss budget while providing spectrally efficient modulation for data rates of 100Gb/s/wavelength.

UCL PI: Georgios Zervas (opens in new tab)

Microsoft PI: Paolo Costa

UCL Student: Alessandro Ottino (opens in new tab)

In the last few years the demand for Machine Learning (ML) and Artificial Intelligence (AI) has experienced an unprecedented growth due to the improvement and availability of hardware accelerators. To increase the prediction capabilities and applications of deep learning models, deeper and larger models trained with larger amount of data are needed. The requirements of these new models is outpacing the hardware improvement, forcing scientists to rely on distributing the ML workload onto multiple accelerators instead of a single one. Scaling these distributed-training workloads is often limited by communication/ computation time imbalance, making the network one of the key bottlenecks. The goal of this project is to investigate how novel optics technologies could address these challenges by rethinking the network from the grounds up and purposely optimizing it for distributed training.

UCL PI: Zhixin Liu (opens in new tab)

Microsoft PIs: Hitesh Ballani, Paolo Costa

UCL Student: Kari Clark (opens in new tab)

The rapid growth in the amount of data being transferred within data centres, combined with the slowdown in Moore’s Law, creates challenges for the future scalability of electronically switched data-centre networks. Optical switches could offer a future-proof alternative, and photonic integration platforms have been demonstrated with nanosecond-scale optical switching times. End-to-end switching time is, however, currently limited by the clock and data recovery time, which typically takes microseconds, removing the benefits of nanosecond optical switching. Here we show that a clock phase caching technique can provide clock and data recovery times of under 625 ps (16 symbols at 25.6 Gb s−1). Our approach uses the measurement and storage of clock phase values in a synchronized network to simplify clock and data recovery versus conventional asynchronous approaches. We demonstrate the capabilities of our technique using a real-time prototype with commercial transceivers and validate its resilience against temperature variation and clock jitter.

UCSB PI: Dan Blumenthal (opens in new tab)

Microsoft PI: Hitesh Ballani

UCSB Students: Grant Brodnik (opens in new tab), Mark Harrington (opens in new tab)

As data center ethernet switches scale toward 100 Tbps, the fiber interconnect will face significant cost, power, and engineering barriers. We describe FRESCO, a fiber data center interconnect (DCI) that brings high order coherent WDM Terabit links inside the data center without the need for DSP and other power consuming technologies. FRESCO replaces high power DSP- and PLL-based carrier phase recovery by employing integrated ultra-low linewidth stimulated Brillouin scattering (SBS) 1550nm lasers stabilized to reference µ-cavities for ~1Hz fundamental linewidth and 10s of Hz integral linewidth optical carriers. This enables the optical frequency stabilized phase locked loop (OFS-PLL) using low bandwidth (<1MHz), low power simple electronics to achieve a direct optical carrier lock with residual phase error variance of 3×10-4 rad2, sufficient for high-order QAM. The architecture is extended to shared source WDM operation using Kerr soliton optical frequency comb generators, amortizing cost and complexity over all channels. Fully integrated silicon photonic transceivers offer reduced footprint and power consumption.

To date, we have demonstrated a discrete component single channel 50Gbd 16-QAM FRESCO link using the DSP-free OFS-PLL with low bandwidth (<1MHz), low power electronics for carrier phase recovery over a 200m fiber channel achieving EVM performance within ~1% of a DSP based reference link. We have also demonstrated generation of an ultra-low linewidth WDM shared source using the frequency stabilized SBS laser to pump a Kerr soliton in a SiN microring. Operation as a shared source architecture offers unique opportunities for power savings and motivates current efforts in modeling the impact of stable, ultra-low phase noise optical sources on link performance and power consumption. With our proposed DSP-free architecture, demands on data-chain electronics such as DACs and ADCs may be relaxed, offering additional power savings for tomorrow’s hyperscale DCIs. Future experimental efforts will scale baudrate, QAM order, and WDM count approaching energy efficiency below 10pJ /bit and 10s of Terabits link capacity.

CU PIs: Richard Penty (opens in new tab), Nikos Bamiedakis (opens in new tab)

Microsoft PI: Fotini Karinou

CU Student: Arastu Sharma (opens in new tab)

Incorporating optics in close proximity to high-performance electronic chips on the board-level can not only allow substitution of the existing electrical connections with faster, more power-efficient alternatives, but most importantly, the radical re-design of the system architecture and yet has had limited exploration. Performance of optical links have interdependence on the link utilisation by the application traffic, which makes optical design space a multi-dimensional challenge. We need a solution that looks at the problem from different perspectives, and considers all aspects including the allocation of system resources, technologies and network topology for different applications. Through our study we want to develop a tool that can help in quantifying these design trade-offs, which will in turn help us in designing optimal architectures functioning with high bandwidth, energy efficient optical links. In this project therefore, we study various board-level interconnection architectures for multiple computing chips using on-board optics taking into account recent achievements in the field. To conduct a performance metric simulation, we input our designs into an architecture simulator in combination of an opto-electronic device modelling tool and run for standard workload benchmarks. We compare our design trade-offs with respect to each architecture based on the different available technologies and derive the optimum configuration for execution time, power consumption and implementation complexity.

CU PI: Daping Chu (opens in new tab)

Microsoft PI: James Clegg, Andreas Georgiou

CU Student: Jintao Hong (opens in new tab)

A low-cost Liquid Crystal display can modulate the polarization of more than 2 billion of pixels per second. These devices are everywhere, from our smartphones, digital cameras and smart watches and provide the highest electro-optical modulation bandwidth in consumer products. When used in a birefringence-based optical data storage system (like Project Silica), they can enable highly parallel data writing making opto-mechanics simpler and relaxing the femtosecond laser requirements. Nevertheless, there are still many challenges including (a) splitting the laser beam and controlling the polarization of each beam (b) controlling the amplitude of the un-modulated light and (c) ensuring the multiple beams are all tightly focused in the glass.

UO PI: Harish Bhaskaran

Microsoft PI: Francesca Parmigiani

The use of functional materials that can accumulate information to carry out both memory and computing tasks in-situ is a growing field. Using optical integration onto silicon chips provides a unique opportunity to combine the benefits of silicon scaling and the wavelength multiplexing of optics onto a single platform. In this proposal, we will significantly expand our initial work on carrying out non-von Neumann computations (such as Vector-Matrix Multiplication directly in hardware) to a larger matrix to prove a lab scale demonstration of the potential for such hardware in real-world computing tasks. In addition, this proposal will aim to benchmark such computations against existing state-of-the-art in terms of energy and operational speed.