eMIPS

Have you ever thought of building your own processor or maybe just defining your own machine instructions? With eMIPS now you can.

The “extensible MIPS” is a dynamically extensible processor architecture that realizes the performance benefits of application-specific hardware optimizations in a safe, general-purpose, multi-user system environment. It allows multiple secure Extensions to load dynamically and to plug into the stages of a pipelined data path, thereby extending the core instruction set of the microprocessor. Extensions can also be used to realize on-chip peripherals and if area permits even multiple cores. Extended Instructions can dramatically speedup application programs just by patching their binaries. The first eMIPS prototype was built out of a Xilinx FPGA using the ML401 board. It booted a small OS and ran real programs. The current version runs NetBSD on the Xilinx ML402 and XUP boards, as well as on the BEE3 system.

The original release of eMIPS is still available here (9MB zip file). The latest release is now an official Microsoft download, and is available here (23MB msi file). A slide deck with a project summary is here (2MB ppt file). A discussion forum for eMIPS users and friends is here.

There are a few tools included in the release and others are separately available.

The PSL-to-Verilog (P2V) compiler generates Verilog monitors for assertion based verification of software, with zero overhead. The first release of P2V is here (650 KB msi installer file).

eBug provides the benefits of hardware-level debugging (e.g. JTAG style) within the safe limits of a software process. It is included in the eMIPS release.

The MIPS-to-Verilog (M2V) compiler generates application-specific extended instructions. It translates the binary instructions of a set of MIPS basic blocks into Verilog. It is available as part of the latest release of the Giano simulator here.

The BBTOOLS are a set of programs for extracting the basic blocks from program binaries, working with performance profiles in concert with the Giano simulator, and patching the binaries with the Extended instructions. They are also part of the Giano distribution.

The manual for the first release is available here. It still contains some valuable bits of information.   The manual for the current release is available here.

The papers below describe in more details what these tools do and how, as well as other eMIPS-related projects.

Operating system software for eMIPS includes a Real-Time OS and NetBSD. Any compiler than can generate code for the original MIPS processor will work with eMIPS also.

The Microsoft Invisible Computing RTOS is available here, instructions for using it on an eMIPS system (such as the XUP board) are included in the user manual for the eMIPS system.

NetBSD version 4.0.1 has been ported to eMIPS and is available here. NetBSD includes its own compiler. Instructions for using NetBSD, both on the Giano simulator and the XUP board, are included in this technical report.

Papers

1. Pittman, R. N., Lynch, N. L., Forin, A. eMIPS, A Dynamically Extensible Processor, MSR-TR-2006-143, Microsoft Research, WA, October 2006.
2. Lu, H., Forin, A. The Design and Implementation of P2V, An Architecture for Zero-Overhead Online Verification of Software Programs, MSR-TR-2007-99, Microsoft Research, WA, August 2007. Presented at the 5th Workshop on Application Specific Processors, Salzburg, Austria, October 2007. Updated version appeared in Transactions on VLSI, November 2008.
3. Sukhwani, B., Forin, A., Pittman, R. N. Extensible On-Chip Peripherals, MSR-TR-2007-120, Microsoft Research, WA, September 2007. Presented at the 16th Symposium on Field-Programmable Custom Computing Machines, Stanford, CA, April 2008. Extended version at the 6th Symposium on Application Specific Processors, Anaheim, CA, June 2008.
4. Meier, K., Forin, A. MIPS-to-Verilog, Hardware Compilation for the eMIPS Processor, MSR-TR-2007-128, Microsoft Research, WA, September 2007. Presented at the 16th Symposium on Field-Programmable Custom Computing Machines, Stanford, CA, April 2008.
5. Busonera, G., Forin, A. eBug: Debugging Extensions for the eMIPS Dynamically Extensible Processor., MSR-TR-2007-155, Microsoft Research, WA, November 2007. Presented at the 8th Symposium on Sytems, Architectures, Modeling and Simulation, Samos, Greece, July 2008.
6. Sekar, A., Forin, A. Automatic Generation of Interrupt-Aware Hardware Accelerators with the M2V Compiler., MSR-TR-2008-110, Microsoft Research, WA, August 2008. Presented at Workshop on Soft Processor Systems (17th PACT), Toronto, ON, Canada, October 2008.
7. Carver, J., Pittman, R. N., Forin, A. Relocation and Automatic Floor-planning of FPGA Partial Configuration Bit-Streams, MSR-TR-2008-111, Microsoft Research, WA, August 2008. Presented at the 17th Symposium on Field-Programmable Gate Arrays, Monterey, CA, February 2009.
8. Pittman, R. N., Forin, A. A Security Model for Reconfigurable Microcomputers, MSR-TR-2008-121, Microsoft Research, WA, September 2008. Presented at the 3rd Workshop on Embedded Systems Security. Atlanta, GA, October 2008.
9. Sirowy, S., Forin, A. Where’s the Beef? Why FPGAs Are So Fast, MSR-TR-2008-130, Microsoft Research, WA, September 2008. Presented at the International Conference on Engineering of Reconfigurable Systems and Applications (ERSA), Las Vegas, NV, July 2009.
10. Sheldon, D., Forin, A. An online scheduler for hardware accelerators on general-purpose operating systems, MSR-TR-2009-41, Microsoft Research, WA, 2009. Poster at the 17th Symposium on Field-Programmable Custom Computing Machines, Napa, CA, April 2009.
11. Chen, Z., Pittman, R. N., Forin, A. Multicore eMIPS, MSR-TR-2009-113, Microsoft Research, WA, August 2009. Presented at the 18th Symposium on Field-Programmable Gate Arrays, Monterey, CA, February 2010.
12. Jin, Z., Pittman, R. N., Forin, A. Reconfigurable Custom Floating-Point Instructions, MSR-TR-2009-157, Microsoft Research, WA, August 2009. Presented at the 18th Symposium on Field-Programmable Gate Arrays, Monterey, CA, February 2010.
13. Liu, S., Pittman, R. N., Forin, A. Energy Reduction with Run-Time Partial Reconfiguration, MSR-TR-2009-2017, Microsoft Research, WA, September 2009. Presented at the 18th Symposium on Field-Programmable Gate Arrays, Monterey, CA, February 2010. Revised for the 21st International Conference on Application-specific Systems, Architectures and Processors, Rennes, France, July 2010.
14. Liu, S., Pittman, R. N., Forin, A. Minimizing Partial Reconfiguration Overhead with Fully Streaming DMA Engines and Intelligent ICAP Controller, MSR-TR-2009-150, Microsoft Research, WA, September 2009. Presented at the 18th Symposium on Field-Programmable Gate Arrays, Monterey, CA, February 2010.
15. Gu, R.,  Forin, A., Pittman, R. N. Path-Based Scheduling in a Hardware Compiler, MSR-TR-2009-106, Presented at the International Conference on Design Automation and Test in Europe (DATE’10), Dresden, Germany, March 2010.
16. Li, W., Forin, A. Specification Mining for Digital Circuits with Applications on Verification and Diagnosis, MSR-TR-2009-114, Microsoft Research, WA, August 2009. Extended version To be Presented at the 47th Design Automation Conference, Anaheim, CA, June 2010.

• Nathaniel L. Lynch
• Hong Lu
• Bharat Sukhwani
• Karl Meier
• Giovanni Busonera
• Abilash Sekar
• Jeff Carver
• Scott Sirowy
• David Sheldon
• Zhimin Chen
• Zhanpeng Jin
• Shaoshan Liu
• Wenchao Li
• Ruirui Gu